View CY7C1079DV33_8977724.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

CY7C1079DV33 32-mbit (4 m 8) static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-50282 rev. *d revised april 27, 2011 32-mbit (4 m 8) static ram features high speed ? t aa = 12 ns low active power ? i cc = 250 ma at 12 ns low cmos standby power ? i sb2 = 50 ma operating voltages of 3.3 0.3 v 2.0 v data retention automatic power down when deselected ttl compatible inputs and outputs available in pb-free 48-ball fbga package functional description the CY7C1079DV33 is a high per formance cmos static ram organized as 4,194,304 words by 8 bits. to write to the device, take chip enable (ce [1] ) and write enable (we ) input low. data on the eight i/o pins (i/o 0 through i/o 7 ) is then written into the location specified on the address pins (a 0 through a 21 ). to read from the device, take chip enable (ce [1] ) low and output enable (oe ) low while forcing the write enable (we ) high. under these conditions, the contents of the memory location specified by the address pins appear on the i/o pins. see truth table (single chip enable) on page 9 for a complete description of read and write modes. the input and output pins (i/o 0 through i/o 7 ) are placed in a high impedance state when the device is deselected (ce [1] high), the outputs are disabled (oe high), or during a write operation (ce [1] low and we low). the CY7C1079DV33 is available in a 48-ball fbga package. logic block diagram 15 16 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 column decoder row decoder sense amps input buffer 4m x 8 array a 0 a 12 a 14 a 13 a a a 17 a 18 a 10 a 11 io 0 ? io 7 oe we ce a 9 a 19 a 20 a 21 [1] note 1. bga packaged device is offered in single ce and dual ce options. in this data sheet, for a dual ce device, ce refers to the internal logical combination of ce 1 and ce 2 such that when ce 1 is low and ce 2 is high, ce is low. for all other cases ce is high. [+] feedback
CY7C1079DV33 document number: 001-50282 rev. *d page 2 of 14 contents selection guide ................................................................ 3 pin configuration ............................................................. 3 maximum ratings ............................................................. 4 operating range ............................................................... 4 dc electrical characteristics .......................................... 4 capacitance ...................................................................... 5 thermal resistance .......................................................... 5 data retention characteristics ....................................... 5 ac switching characteristics ......................................... 6 switching waveforms ...................................................... 7 truth table (single chip enable) .................................... 9 truth table (dual chip enable) ....................................... 9 ordering information ...................................................... 10 ordering code definitions ..... .................................... 10 package diagrams .......................................................... 11 acronyms ........................................................................ 12 document conventions ................................................. 12 units of measure ....................................................... 12 document history page ................................................. 13 sales, solutions, and legal information ...................... 14 worldwide sales and design s upport ......... .............. 14 products .................................................................... 14 psoc solutions ......................................................... 14 [+] feedback
CY7C1079DV33 document number: 001-50282 rev. *d page 3 of 14 selection guide description ?12 unit maximum access time 12 ns maximum operating current 250 ma maximum cmos standby current 50 ma pin configuration figure 1. 48-ball fbga (single chip enable) [2] figure 2. 48-ball fbga (dual chip enable) [2] we a 11 a 10 a 6 a 0 a 3 ce nc nc io 0 a 4 a 5 io 1 nc io 2 io 3 nc v ss a 9 a 8 oe a 7 nc nc nc a 17 a 2 a 1 nc io 4 nc io 5 io 6 nc io 7 nc a 15 a 14 a 13 a 12 a 21 a 19 a 20 3 26 5 4 1 d e b a c f g h a 16 a 18 v cc v cc v ss we a 11 a 10 a 6 a 0 a 3 ce 1 nc nc io 0 a 4 a 5 io 1 nc io 2 io 3 nc v ss a 9 a 8 oe a 7 nc nc ce 2 a 17 a 2 a 1 nc io 4 nc io 5 io 6 nc io 7 nc a 15 a 14 a 13 a 12 a 21 a 19 a 20 3 26 5 4 1 d e b a c f g h a 16 a 18 v cc v cc v ss note 2. nc pins are not connected to the die. [+] feedback
CY7C1079DV33 document number: 001-50282 rev. *d page 4 of 14 maximum ratings exceeding maximum ratings may shorten the useful life of the device. these user guidelines are not tested. storage temperature .... ............ ............... ?65 ? c to +150 ? c ambient temperature with power applied .... .............. .............. .......... ?55 ? c to +125 ? c supply voltage on v cc relative to gnd [3] ..?0.5 v to +4.6 v dc voltage applied to outputs in high z state [3] ................................. ?0.5 v to v cc + 0.5 v dc input voltage [3] ............................. ?0.5 v to v cc + 0.5 v current into outputs (low)..... .................................... 20 ma static discharge voltage.......................................... > 2001 v (mil-std-883, method 3015) latch up current .................................................... > 200 ma operating range range ambient temperature v cc industrial ?40 ? c to +85 ? c 3.3 v ? 0.3 v dc electrical characteristics over the operating range parameter description test conditions ? 12 unit min max v oh output high voltage v cc = min, i oh = ?4.0 ma 2.4 ? v v ol output low voltage v cc = min, i ol = 8.0 ma ? 0.4 v v ih input high voltage 2.0 v cc + 0.3 v v il input low voltage [3] ?0.3 0.8 v i ix input leakage current gnd < v i < v cc ?1 +1 ? a i oz output leakage current gnd < v out < v cc , output disabled ?1 +1 ? a i cc v cc operating supply current v cc = max, f = f max = 1/t rc, i out = 0 ma cmos levels ?250ma i sb1 automatic ce power down current ? ttl inputs max v cc , ce [4] > v ih , v in > v ih or v in < v il , f = f max ?60ma i sb2 automatic ce power down current ?cmos inputs max v cc , ce [4] > v cc ? 0.3 v, v in > v cc ? 0.3 v, or v in < 0.3 v, f = 0 ?50ma notes 3. v il (min) = ?2.0 v and v ih (max) = v cc + 2 v for pulse durations of less than 20 ns. 4. bga packaged device is offered in single ce and dual ce options. in this data sheet, for a dual ce device, ce refers to the internal logical combination of ce 1 and ce 2 such that when ce 1 is low and ce 2 is high, ce is low. for all other cases ce is high. [+] feedback
CY7C1079DV33 document number: 001-50282 rev. *d page 5 of 14 notes 5. valid sram operation does not occur until the power supplies have reached the minimum operating v dd (3.0 v). 100 ? s (t power ) after reaching the minimum operating v dd , normal sram operation begins including reduction in v dd to the data retention (v ccdr , 2.0 v) voltage. 6. bga packaged device is offered in single ce and dual ce options. in this data sheet, for a dual ce device, ce refers to the internal logical combination of ce 1 and ce 2 such that when ce 1 is low and ce 2 is high, ce is low. for all other cases ce is high. 7. tested initially and after any design or proce ss changes that may affect these parameters. 8. full device operation requires linear v cc ramp from v dr to v cc(min.) > 50 ? s or stable at v cc(min.) > 50 ? s. capacitance tested initially and after any design or proces s changes that may affect these parameters. parameter description test conditions 48-ball fbga unit c in input capacitance t a = 25 ? c, f = 1 mhz, v cc = 3.3 v 16 pf c out i/o capacitance 20 pf thermal resistance tested initially and after any design or proces s changes that may affect these parameters. parameter description test conditions 48-ball fbga unit ? ja thermal resistance (junction to ambient) still air, soldered on a 3 4.5 inch, four layer printed circuit board 30.91 ? c/w ? jc thermal resistance (junction to case) 13.60 ? c/w figure 3. ac test loads and waveforms [5] data retention characteristics over the operating range parameter description conditions min typ max unit v dr v cc for data retention 2 ? ? v i ccdr data retention current v cc = 2 v, ce [6] > v cc ? 0.2 v, v in > v cc ? 0.2 v or v in < 0.2 v ?? 50 ma t cdr [7] chip deselect to data retention time 0 ? ? ns t r [ 8] operation recovery time t rc ??ns figure 4. data retention waveform 90% 10% 3.0 v gnd 90% 10% all input pulses 3.3 v output 5 pf* including jig and scope (b) r1 317 ? r2 351 ? rise time > 1 v/ns fall time: > 1 v/ns (c) output 50 ? z 0 = 50 ? v th = 1.5 v 30 pf* * capacitive load consists of all components of the test environment high-z characteristics (a) 3.0 v 3.0 v t cdr v dr > 2 v data retention mode t r ce [6] v cc [+] feedback
CY7C1079DV33 document number: 001-50282 rev. *d page 6 of 14 ac switching characteristics over the operating range [9] parameter description ? 12 unit min max read cycle t power v cc (typical) to the first access [10] 100 ? ? s t rc read cycle time 12 ? ns t aa address to data valid ? 12 ns t oha data hold from address change 3 ? ns t ace ce [11] low to data valid ? 12 ns t doe oe low to data valid ? 7 ns t lzoe oe low to low z 1 ? ns t hzoe oe high to high z [12] ?7 ns t lzce ce low to low z [11, 12] 3? ns t hzce ce high low to high z [11, 12] ?7 ns t pu ce low high to power up [11, 13] 0? ns t pd ce high low to power down [11, 13] ?12 ns write cycle [14, 15] t wc write cycle time 12 ? ns t sce ce [11] low high to write end 9 ? ns t aw address setup to write end 9 ? ns t ha address hold from write end 0 ? ns t sa address setup to write start 0 ? ns t pwe we pulse width 9 ? ns t sd data setup to write end 7 ? ns t hd data hold from write end 0 ? ns t lzwe we high to low z [12] 3? ns t hzwe we low to high z [12] ?7 ns notes 9. test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 v, and input pulse levels of 0 to 3.0 v. test conditions for the read cycle use output loading shown in part a) of figure 3 on page 5 , unless specified otherwise. 10. t power gives the minimum amount of time that the power supply is at typical v cc values until the first memory access is performed. 11. bga packaged device is offered in single ce and dual ce options. in this data sheet, for a dual ce device, ce refers to the internal logical combination of ce 1 and ce 2 such that when ce 1 is low and ce 2 is high, ce is low. for all other cases ce is high. 12. t hzoe , t hzce , t hzwe , t lzoe , t lzce , and t lzwe are specified with a load capacitance of 5 pf as in (b) of figure 3 on page 5 . transition is measured ? 200 mv from steady state voltage. 13. these parameters are guaranteed by design and are not tested. 14. the internal write time of the memory is defined by the overlap of we , ce = v il . ce and we are low to initiate a write, and the transition of any of these signals can terminate. the input data setup and hold timing should be refe renced to the edge of the signal that terminates the write. 15. the minimum write cycle time for write cycle no. 2 (we controlled, oe low) is the sum of t hzwe and t sd . [+] feedback
CY7C1079DV33 document number: 001-50282 rev. *d page 7 of 14 switching waveforms figure 5. read cycle no. 1 [16, 17] figure 6. read cycle no. 2 (oe controlled) [17, 18, 19] previous data valid data valid rc t aa t oha t rc address data out notes 16. the device is continuously selected. ce = v il . 17. we is high for read cycle. 18. bga packaged device is offered in single ce and dual ce options. in this data sheet, for a dual ce device, ce refers to the internal logical combination of ce 1 and ce 2 such that when ce 1 is low and ce 2 is high, ce is low. for all other cases ce is high. 19. address valid before or similar to ce transition low. 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t pd t hzce oe ce address data out v cc supply current high impedance i cc i sb [+] feedback
CY7C1079DV33 document number: 001-50282 rev. *d page 8 of 14 figure 7. write cycle no. 1 (ce controlled) [20, 21, 22] figure 8. write cycle no. 2 (we controlled, oe low) [20, 21, 22] switching waveforms (continued) t hd t sd t sce t sa t ha t aw t pwe t wc data i/o address ce we t hd t sd t sce t ha t aw t pwe t wc t sa t lzwe t hzwe data i/o address ce we notes 20. bga packaged device is offered in single ce and dual ce options. in this data sheet, for a dual ce device, ce refers to the internal logical combination of ce 1 and ce 2 such that when ce 1 is low and ce 2 is high, ce is low. for all other cases ce is high. 21. data i/o is high impedance if oe = v ih . 22. if ce goes high simultaneously with we going high, the output remains in a high impedance state. [+] feedback
CY7C1079DV33 document number: 001-50282 rev. *d page 9 of 14 truth table (single chip enable) ce [1] oe we i/o 0 ? i/o 7 mode power h x x high z power down standby (i sb ) l l h data out read all bits active (i cc ) l x l data in write all bits active (i cc ) l h h high z selected, outputs disabled active (i cc ) truth table (dual chip enable) ce 1 ce 2 oe we i/o 0 ? i/o 7 mode power h x x x high z power down standby (i sb ) x l x x high z power down standby (i sb ) l h l h data out read all bits active (i cc ) l h x l data in write all bits active (i cc ) l h h h high z selected, outputs disabled active (i cc ) [+] feedback
CY7C1079DV33 document number: 001-50282 rev. *d page 10 of 14 ordering information speed (ns) ordering code package diagram package type operating range 12 CY7C1079DV33-12baxi 51-8 5191 48-ball fbga (8 9.5 1.2 mm) (pb-free) [23] industrial 12 CY7C1079DV33-12b2xi 51-85191 48-ball fbga (8 9.5 1.2 mm) (pb-free) [24] industrial contact sales for part availability. ordering code definitions temperature range: i = industrial package type: xxx = bax or b2x bax = 48-ball fbga (pb-free) - single chip enable b2x = 48-ball fbga (pb-free) - dual chip enable speed: 12 ns v33 = voltage range (3 v to 3.6 v) d = c9, 90 nm technology 9 = data width 8-bits 07 = 32-mbit density 1 = fast asynchronous sram family technology code: c = cmos 7 = sram cy = cypress c cy 1 - 12 xxx 7 07 d i v33 9 notes 23. this bga package is offered with single chip enable. 24. this bga package is offered with dual chip enable. [+] feedback
CY7C1079DV33 document number: 001-50282 rev. *d page 11 of 14 package diagrams figure 9. 48-ball fbga (8 9.5 1.2 mm), 51-85191 51-85191 *a [+] feedback
CY7C1079DV33 document number: 001-50282 rev. *d page 12 of 14 acronyms document conventions units of measure acronym description ce chip enable cmos complementary metal oxide semiconductor fpbga fine-pitch ball grid array i/o input/output oe output enable sram static random access memory ttl transistor transistor logic we write enable symbol unit of measure ns nano seconds vvolts a micro amperes s micro seconds mv milli volts ma milli amperes ms milli seconds mm milli meter mhz mega hertz pf pico farad wwatts % percent ? ohms c degree celcius [+] feedback
CY7C1079DV33 document number: 001-50282 rev. *d page 13 of 14 document history page document title: CY7C1079DV33 32-mbit (4 m 8) static ram document number: 001-50282 rev. ecn no. submission date orig. of change description of change ** 2711136 05/29/2009 vkn/pyrs new data sheet added -45b2xi part (dual ce option) *a 2759408 09/03/2 009 vkn/aesa removed 10ns speed marked thermal specs as ?tbd? changed t doe , t hzoe , t hzce , t hzwe specs from 6 ns to 7ns added -12b2xi part (dual ce option) *b 2813370 11/23/2009 vkn changed i cc spec from 225 ma to 250 ma *c 3132969 01/11/2011 pras added ordering code definitions . updated package diagrams . added acronyms and units of measure . changed all instances of io to i/o. updated in new template. *d 3232668 04/18/2011 pras changed status from preliminary to final. updated pin configuration ( figure 2 ). updated thermal resistance . [+] feedback
document number: 001-50282 rev. *d revised april 27, 2011 page 14 of 14 all products and company names mentioned in this document may be the trademarks of their respective holders. CY7C1079DV33 ? cypress semiconductor corporation, 2009-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress.com/sales. products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback

▲Up To Search▲

Price & Availability of CY7C1079DV33

	To Download CY7C1079DV33 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .